Questions? Feedback? powered by Olark live chat software

The cookie settings on this website are set to 'allow all cookies' to give you the very best experience. Please click Accept Cookies to continue to use the site.

A Quick Guide to Memory Rank

Posted by Integrity Global on Feb 9th 2018

A Quick Guide to Memory Rank

Memory Rank Decoder

Memory rank, like in the picture above, has two distinct components. The first part of the memory rank equation deals with how the computer processes information or data through the memory; for example single rank (1R), dual rank (2R), quad rank (4R) or octet rank (8R). How your computer handles rank is that each processor has a maximum number of ranks available to each memory channel. Each rank operates similarly to a multi-lane highway, where vehicles can take up one, two, or four lanes on the highway to transfer data. Once you fill all the lanes, adding more memory is not possible. If the total number of ranks in the populated DIMM slots exceeds the number of loads the chipset can support, the server may not boot properly or operate correctly.

The second component of rank is the data bit width of the memory like x4 or x8. For example, x8 DRAMS usually consist of 8 chips (9 if it’s ECC memory), and x4 would have 16 chips (18 if it’s ECC memory). The additional chips on ECC memory are there to help process the detecting and correcting of single bit errors and multiple-bit errors.

To make the memory as cost-effective as possible while maintaining performance, memory manufacturers try to pack as many chips onto a single module as they possibly can. To do this, they need to use multiple memory ranks to allow high-speed access to all the memory. To make high capacity memory modules (16GB or higher) memory manufacturers will sometimes use four ranks per memory module. If you look at the new octal chips from HPE like the 128GB kits for the Gen 10 servers, they have special load reducing technology to help achieve higher capacities.

A practical application of rank would look like this:

  • An HP DL380 G7 supports 5520 series Intel Processors
  • 5520 series processors all have a maximum of 8 ranks per memory channel
  • Xeon 55\56xx series processors have three memory channels that support three DIMM slots
  • Since the CPU's only support three channels this is why if you have one processor you have 9 memory slots and for two processors you have18 memory slots
  • If you add 9 registered ECC single rank DIMMs in a single processor system, you are only using 3/8 ranks per channel
  • If you add 9 registered ECC dual rank DIMMs in a single processor system, you are only using 6/8 ranks per channel
  • You cannot add 9 registered ECC quad-rank DIMMs in a single processor system because that would be 12/8 ranks. The most you could add would be 6.

Load Reduced memory has an extra chip on the memory module that multiplies a memory rank. The chip on the module tells the server that it only needs one or two ranks, but handles four (or more) actual ranks on the memory module. By doing this, you can pack even higher densities onto a single DIMM. However, you are still unable to mix different memory types.

As demands for even more memory in a system increases, memory manufacturers get even more creative about packing more memory chips onto a single memory module. The most recent technology is 3D Load Reduced memory. In this design, memory modules are designed to be stacked on top of each other and pass their wiring through to the base memory module allowing at least twice as many chips on the same size memory module as before. As technologies allow for higher densities of memory per chip, expect the maximum memory per stick to continue to increase.